Storage Informer
Storage Informer

Introducing Parallelism to University Faculty in Illinois

by on Jul.23, 2009, under Storage

Introducing Parallelism to University Faculty in Illinois

I just completed giving a two-day training course to introduce university faculty to what courseware materials are available from the Intel Academic Community. Another goal of the training is to give faculty an introduction to parallel and threaded programming the latest technology available for writing such applications.


I was helped out by Jay Desouza (middle) and Jackson Marusarz (left), both colleagues here at Intel in Champaign, Illinois. The course was held on the University of Illinois, Urbana-Champaign, campus. Jay did an excellent job with the lectures in his first stint with the Innovative Software Education material.

We presented the "standard" types of material: OpenMP 3.0, debugging and tuning threaded code with Intel Parallel Studio, threaded programming methodology, and Intel Threading Building Blocks. Labs go along with these modules, so everyone got a hands-on chance at parallel programming. There were some technical issues with the equipment and presentation materials at times, but we were able to muddle through.

The UPCRC folks at UIUC played host to our training sessions. They had things well in hand (they printed the poster in the picture) and the event ran smoothly on their end. They even went above and beyond by staging a panel discussion with some of the faculty.

The discussion was centered around what kinds of experieinces the UIUC professors have gone through in the attempt to bring parallelism into their curriculum. One of the points that I had not considered before was that students need to have a modicum of computer architecture knowledge to understand why parallel applications perform well or what kinds of performance issues might be caused by the interaction of the threads in the parallel algorithm executing on a processor. How can we hope students will understand what false sharing is and why it should be avoided if they don&apost understand the reality of cache line size or how those lines are treated in modern processors?

I&aposve gone through several Computer Science degree programs, so this kind of knowledge has become second nature to me. However, it&aposs not until students take a course in computer architecture and organization that some of these ideas are presented. (In fact, there is no point within most CS curriculums where program debugging and optimization is a topic of instruction.) The panel discussion made me realize that if we&aposre going to make parallelism more prevalant, especially for students that aren&apost trying to get a CS degree, we need to give them some background about five to six key computer architecture topics to understand serial and, consequently, parallel performance optimization. Scalability of application performance beyond 4 cores is going to require a slightly more intimate knowledge of things like the memory hierarchy of a platform.

Overall, the class was a success. I got to sleep in my own bed each night after class and didn&apost have to sit on a plane for 6 or more hours. If only they were all this easy. :-)

URL: http://feedproxy.google.com/~r/IntelBlogs/~3/artUeGx14wE/

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