Storage Informer
Storage Informer

Making of Core i7 — What’s Next?

by on Aug.19, 2009, under Storage

Making of Core i7 — What’s Next?

Nehalem played a big role during IDF 2008. Many new details were introduced during keynotes and in briefings, including features built into the microarchitecture like Turbo Mode, which allow the cores to dynamically scale up to handle demanding needs like video encoding or scale down to use just enough of a core to finish a simple task like typing.

Just after IDF 2008 in San Francisco, we visited some of the engineers who played a role in the making of the Intel Core i7 processor. This video was create just as the first Nehalem designed processors for consumers were about to hit the market. We visited design and testing labs in Hillsboro, Oregon and Santa Clara, California.

As we get closer to IDF 2009 in San Francsico, we¡¦ll be visiting with manufacturing, design and test engineers working away on what¡¦s next¡Kcodename Westmere.

Where Nehalem was new chip archeticture design, Westmere is the next design being used to build processors that feature two 32nm cores with 4MB of cache that sit next to a memory controller and integrated graphics built on a separate, neighboring 45nm chip, all in one package. Westmeres will be the basis of upcoming all new Core chips (Core i3, i5, and 7) over the next few months.

Westmere processors will share some of the same features that were built into Nehalem, including Hyper-Threading and Turbo Boost (descirbed above).

Some Westmeres will feature HyperThreading will allow each core to handle two threads ¡X or process two jobs at once.

As we work on the ¡§Making of¡¨ Westmere video prior to IDF, here is a video I shot with Intel¡¦s Steve Smith, as he prepared for the first public demonstation of a Westmere-designed chip earlier this year.

If you¡¦d like to follow the integration and innovation stories leading up to, during and after the Intel Developer Forum (September 22-24 in San Francisco), please follow:

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