Storage Informer
Storage Informer

Tag: IBM

IWJT, Expo 2010 and Shanghai, China

by on Jul.01, 2010, under Storage

IWJT, Expo 2010 and Shanghai, China

I’ve recently returned from the International Workshop on Junction Technology in Shanghai China. Shanghai is a fascinating city (or mega-city). The Chinese say that Xian is the city of the past, Beijing is the city of the present and Shanghai is the city of the future. I certainly agree with that characterization of Shanghai! From the LED-dominated night skyline to the new high-speed maglev train – Shanghai truly is the city of the future.

 (Picture from left to right is Sadanand Deshpande of IBM,  Raj Jammy of Sematech, Kelin Kuhn of Intel and Yun Wang of Ultratech).

 

The International Workshop on Junction Technology (IWJT) is a critical conference for the implant and annealing community. Why do we care? Well, in a modern CMOS device, one of the most critical parameters for improving performance is the parasitic resistance from the channel to the contact (see Figure, left). This parasitic resistance is the sum of Racc (the resistance in the source-drain extensions) + Rspreading (the resistance as the current fans out into the epi + Repi (the bulk epi resistance) + Rinterface (the resistance between the epi and the silide) + Rsilicide + Rccontact. IWJT primarily focuses on improving three of these resistance components, Racc, Rinterface and Rsilicide.

 

Racc is the resistance of the source-drain extension.  The percentage impact of Rext has been increasing each generation (see Figure, left). Rext is a very sensitive function of the implant and anneal technology. The goal is to achieve the possible junction depth (XJ) with the lowest possible resistance (Racc).   This is achieved by improvements in implant and anneal technology.

 

 

 

 

One of the highlights of the conference was the vigorous discussion on molecular implants (see Figure, left). The key idea with molecular implants is to use a large (or very large) molecule to improve the amorphization, reduce the penetration and increase the dose of the implant into the substrate. One molecular implant (BF2) has been around for a while – but the industry is increasingly moving to much larger molecules such as decaborane, octadecaborane, and carborane. While a number of talks discussed molecular implants, the keynote by Anthony Renau, the modeling study by Takaaki Aoki and the invited paper by Wade Krull all focused significant discussion on the benefits and challenges of molecular implants. 
 

Another of the highlights of the conference was the focused discussion on annealing technology. The key idea with modern annealing technology is to activate the implant with as little subsequent movement of atoms as possible (see Figure, left). While a number of papers discussed anneal technology, the invited papers by Lee on long-mS flash anneals, and Wang on laser annealing all focused significant discussion on the challenges facing anneal technologies in the coming generations.

 

 
While I was in Shanghai, I had the opportunity to visit EXPO 2010 for an afternoon and evening. While I can ramble on indefinitely about the various displays and pavilions, my major geek take-away was that Shanghai must have bought out the market on LED technology. After dark, EVERYTHING seemed to be lit up with complex programmed light shows.  It was virtually impossible to take a bad picture.

 

 

 

Stay tuned.   My next blog (mid-July) is on VLSI!

Comments (0) (closed)

URL: http://feedproxy.google.com/~r/IntelBlogs/~3/Quagtfmw7kg/iwjt_expo_2010_and_shanghai_ch_1.php

Leave a Comment :, , , , , , more...

WaveMaker, Amazon, IBM and RightScale Collaboration Leads To Cloud Quickstart Program

by on Oct.16, 2009, under Storage

WaveMaker, Amazon, IBM and RightScale Collaboration Leads To Cloud Quickstart Program

————————————————————————————————————-

————————————————————̵…

[[ This is a content summary only. Visit my website for full links, other content, and more! ]]

URL: http://feedproxy.google.com/~r/Virtualizationdotcom/~3/l0Q1Ob8WXPc/

Leave a Comment :, , , , , , more...

Michael Dell is Bullish on Nehalem-EX in Oracle Open World Keynote

by on Oct.13, 2009, under Storage

Michael Dell is Bullish on Nehalem-EX in Oracle Open World Keynote

Nehalem-EX has been in the news quite a bit over the past several months. 

First, in May, Intel described how Nehalem-EX will be at the heart of the next generation of intelligent and expandable high-end Intel server platforms, delivering a number of new technical advancements (Intel Nehalem Architecture, Quick Path Interconnects, 16 threads, 24MB cache, new RAS features like MCA-Recovery, 16 DIMM slots per socket, 128 threads on 8 Socket systems) and boost enterprise computing performance (the greatest gain in generational performance ever seen at Intel.)

Next at IDF in September Intel described how Nehalem-EX would deliver a bigger generational performance improvement than that delivered by the Intel Xeon 5500 processor (including a 3X Nehalem-EX gain in database performance); a large shift in Xeon scalability with over 15 >8S systems anticipated and expandability for the most data demanding enterprise applications, the addition of about 20 RAS capabilities traditionally found in the Intel® Itanium processor family – along with a demonstration of MCA-Recovery. IBM announced their upcoming BladeCenter products that will support 4S Nehalem-EX blades and Super-Micro announced a 1U box, specifically targeted at HPC.  Staying on the HPC theme, Mark Seager from the Lawrence Livermore National Laboratory was also quoted with stating that “Nehalem-EX allows us to invest in science, not the computer science of porting and adapting software to new architectures, but real science.  Nehalem EX is an innovative SMP on a chip solution that provides us access to a “super node” … The result is an astonishing new level of performance.”

And Oracle Open World on October 13th, the drumbeat for Nehalem-EX continued.  Michael Dell in his Oracle Open World Keynote today discussed how Nehalem-EX will provide a true leap in performance, with up to 9x the memory bandwidth and 3x the database performance vs. prior generation.  And he mentioned that Dell’s unique implementation of the memory architecture will allow the most cost effective scaling, with 4S systems up to 1TB of DRAM (64 Dimms x 16GB Memory sticks) enabling customers to run their entire database in system memory.  He also mentioned that standard based systems are driving new efficiencies with applications like Oracle, where Dell’s data shows Oracle apps run better on x86 vs. proprietary architectures, up to 200% better. 

Keep your eyes on the Server Room for more Nehalem-EX news as it comes between now and launch.  And visit the Intel booth at South Moscone Booth #1621 to learn more.

Bryce

URL: http://feedproxy.google.com/~r/IntelBlogs/~3/yas-NrX1Z5A/michael-dell-is-bullish-on-nehalem-ex-in-oracle-open-world-keynote

Leave a Comment :, , , , , , , , , , , , , , , , more...

Looking for something?

Use the form below to search the site:

Still not finding what you're looking for? Drop a comment on a post or contact us so we can take care of it!

Visit our friends!

A few highly recommended friends...